This invention relates to the field of semiconductor wafer processing. More particularly the invention relates to a system for improving the electrical characteristics of static random access memory devices.
As semiconductor device geometries shrink, design engineers encounter new problems that tend to reduce the reliability of the devices. In addition, solutions that were developed to overcome previously identified problems may become ineffectual or create other problems as the geometries shrink and other processing constraints change. Thus, there is a continual need to improve upon the methods and structures relied upon in the past.
One issue that is always of high priority is that of maintaining electrical pathway integrity within the device. In other words, ensuring that charge carrier flow is limited to those pathways and those times at which it is desired. For example, it is typically desired to electrically isolate semiconductor devices that are formed adjacent to one another in a semiconducting substrate. This is accomplished in a variety of ways, such as by using locos oxidation or shallow trench isolation techniques. However, as the size of the semiconductor device decreases, the size of these structures must also preferably decrease, which tends to reduce the inherent effectiveness of the isolation structure. This may result in a number of different problems, such as an increase in the soft error rate (SER), where devices become unstable and lose their specified state. Thus, additional systems need to be found to augment the isolation provided by these structures.
As a further example, the ability to open and close the current pathway in a semiconductor device such as a MOS transistor is fundamental to the proper operation of the device. Again, however, as device geometries are reduced, the standard structures that were developed for larger devices tend to be less effectual in preventing inadvertent leakage through the isolation region of smaller transistors. Thus, current interwell punchthrough in the isolation tends to become a bigger problem as the devices are made smaller. Here again, additional systems are needed to augment the strength of the isolation region.
While there may be many systems that could be devised to alleviate these and other problems, they tend to add complexity, expense and time to the device fabrication process. Typically, these added steps come in the form of additional mask layers that must be developed and used. Thus, the financial pressures inherent in semiconductor device fabrication must also be weighed in finding solutions to these conditions.
What is needed, therefore, is a system to improve the soft error rate immunity and isolation punchthrough tolerance of a device, without requiring additional mask layers.
The above and other needs are met by a method for fabricating an SRAM device having a standard well tub, where an additional well tub is deposited within the standard well tub. The additional well tub is deposited to a depth that is shallower than the standard well tub. In this manner, the dopant concentration is increased in the well area of the SRAM device, which increases both the isolation punchthrough tolerance and the SER immunity of the device.
In a preferred embodiment, the additional well tub is deposited using an ion implantation process to a depth that is shallower than the standard well tub. Further, the SRAM device is preferably isolated from adjacent devices with a shallow trench isolation structure that extends to a depth, and the additional well tub is deposited to a depth that is deeper than the depth of the shallow trench isolation structure. In a most preferred embodiment, the additional well tub is implanted using the same mask set as that used for the threshold voltage adjustment deposition of the SRAM device. Thus, in the preferred embodiment, no additional mask layer is required to deposit the additional well tub, and all of the expenses normally associated with an additional mask layer are avoided.